1. Field of the Invention
The present invention relates to a multiprocessor computer system. More specifically, the present invention relates to a system and method for evoking and handling software interrupts in a multiprocessor system.
2. Description of the Related Art
Typical multiprocessor computer systems are composed of a plurality of commercially-available microprocessors. These microprocessors generally have limited functionality supporting synchronization and communication between the multiple processors. Communications between the multiple processors is usually achieved using standard system buses structures such as PCI bus, ISA bus, EISA bus, Ibus, and the like. These bus structures impose a large overhead which slows the communication between the multiple processors in the system.
Using these standard bus structures, software executing on a first processor in the multiprocessor system activates software executing on a second processor through standard hardware interrupt structures associated with the buses and bus interfaces of the multiple processors. Software operating systems controlling multiprocessors have evolved so that a single operating system operates in cooperation on the multiple processors. Thus a highly efficient communication structure would utilize software interrupts rather than hardware interrupts to evoke interrupts in a cooperating processor. However, heretofore software interrupts have been implemented on a single processor so that the interrupt requesting and interrupt handler programs execute on the same processor